1. Field of the Invention
The present invention relates to a parallel flash memory controller, a chip, and a control method thereof. More particularly, the present invention relates to a 2-dimensional (2D) parallel flash memory controller capable of arranging flash memories in channels and rows, flash memory chips, and a control method thereof.
2. Related Art
With the rapid development of PC technology, customers have increasingly high requirements on storage devices, not only in terms of capacity, performance, and speed, but also in power consumption, size, overall external environment and many other requirements concerning special environments. Currently, the storage devices that are most widely used can be generally classified into flash memory devices and hard disk devices according to the type of storage media. As for these two types of storage devices, the hard disk device, due to its lower price, has been more widely adopted than the flash memory device and thus occupies a larger market share. However, the hard disk device still has its own defects, which restricts its applications. For this reason, the flash memory device has gradually replaced the hard disk in some fields, due to certain advantages. The flash memory device has advantages of a fast random read/write speed, stable data resources due to its full-chip operation without mechanical control, low power consumption, high environmental adaptability by taking flash memory chips as the data storage units, and not being easily affected by temperature, air pressure, humidity, and air purity. Thus, flash memory devices have been widely applied. As for the hard disk, due to the internal mechanical structure, it has the defects of large power consumption, large size, noise production, high external environment requirements, and rather low random read/write rate. Therefore, in most applications, the hard disk fails to meet the requirements of the market, and as technology improves, this situation is getting even worse. For example, in portable notebook computers, the hard disk cannot be adapted to such computers due to its defects of large power consumption, poor shock resistance, and large size. Furthermore, in some special environments with higher requirements, the hard disk is restricted by its mechanical structure. However, in such environments, the flash memory shows superiority in performance. On the other hand, the flash memory is also limited in certain applications due to some inherent characteristics. These limitations mainly lie in the fact that the interface read/write rate of the flash memory device cannot be easily increased. As a result, the flash memory is restricted in the field of large-capacity storage devices, especially in those environments requiring a high device read/write rate. Therefore, how to increase the interface read/write rate of the flash memory device is the key point for expanding its potential applications.
Currently, the interface read/write rate of a common flash memory chip reaches up to 10 MBps or around tens of MBps on the average, but the PATA or SATA interface usually adopted by storage devices generally reaches a much higher rate, over 100 MBps on average. Therefore, the interface read/write rate of the flash memory chip is much smaller than that of the device, and the bottleneck of the storage device mainly focuses on the interface read/write rate of the flash memory chip. Therefore, how to effectively raise the interface rate between flash memory chips and its internal controller has become a critical point to the research and development of the flash memory device.
In addition, a multi-channel flash memory processor has appeared on the market. The PRC Patent Publication No. CN1790308A, entitled “Multi-channel Flash Memory Transmission Controller, Chip and Storage Device” puts forward an idea of multi-channel control. However, this patent does not achieve the true multi-channel parallel operation, because the data bandwidth is increased by multiplexing control signal lines of each channel and employing multiple independent data lines. In this way, the above design has the following disadvantages. First, due to the multiplexing of the flash memory feedback signal lines, if one of the flash memory chips fails in operation, all the other sets cannot start the next operation, thereby reducing the working efficiency of the device. Second, as the data operation must be performed on multiple channels at the same time, the circumstances where the operation data is insufficient for four channels to work concurrently may occur repeatedly, which wastes plenty of storage space and shortens the service life of the device when erasing and writing small files frequently. Therefore, though such design can improve the interface bandwidth of the flash memory chip to some extent, its working efficiency is rather low, and at the same time the data transmission rate is much lower than the PATA or SATA interface rate.